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Tensordyne

Sunnyvale, US · 19 known investors

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Tensordyne builds AI hardware, chips, and software systems optimized for efficient inference at reduced energy and computational cost. The company serves organizations seeking advanced AI capabilities with simplified deployment and lower operational overhead.

Also known as Recogni · Tensordyne · Tensordyne (formerly Recogni)

Founders & leadership

RARK Anand
RK AnandCo-founder and Chief Product OfficerRK Anand was a founding engineer at Juniper Networks from 1996, where he spent nearly 17 years working on router architecture and silicon-based forwarding infrastructure. He is now co-founder and Chief Product Officer of Tensordyne, which develops AI hardware and software systems for efficient inference.
GBGilles Backhus
Gilles BackhusCo-Founder, VP of AI & ProductHe has over a decade of experience developing real-time AI systems using FPGAs, microcontrollers, and custom ASICs for automotive, sensor, aerospace, and datacenter applications.
RKR K Anand
R K AnandFounder & Chief Product OfficerR K Anand was a founding engineer at Juniper Networks from 1996 through approximately 2013, where he worked on silicon and hardware-based router forwarding architecture. He is now founder of Tensordyne, which develops AI hardware and software systems for efficient inference.
MBMarc Bolitho
Marc BolithoCEOMarc Bolitho spent 28 years in engineering and business leadership, including as SVP and GM of the ADAS business unit at ZF overseeing 5,000 engineers globally. He is CEO of Tensordyne, which builds AI hardware and software systems optimized for efficient inference at reduced energy and computational cost.

Investors · 19

BMW i Ventureslisted by BMW i VenturesMountain View · $10M

How we know: BMW i Ventures's portfolio page · a partner's Signal profile · funding news · press coverage · Not right? Tell us

Toyota VenturesreportedLos Altos

How we know: the VCSheet dataset · Not right? Tell us

Also in the syndicate · 5

HSBC Innovation BankingMayfieldPledge VenturesSW Mobility FundTasaru Mobility Investments

Funding

SEC filings, press & company announcements

$102M disclosed across 1 of 4 rounds · 2019–2026

Source: company announcements and press reports — follow each round's link for the claim.

Company profile

researched Aug 2026

Tensordyne, previously known as Recogni, develops AI inference hardware and systems built around a proprietary logarithmic-mathematics ("log-math") compute architecture. Its flagship offering is Tensordyne Napier, described by the company as a class of AI inference system combining log-math compute with a low-latency scale-up interconnect to reduce the cost and energy consumption of inference workloads. The Napier platform is presented as a set of components: TDN Math (the numerical approach), TDN AIP (the Napier chip), TDN ACT (the compute tray), and TDN LINK (the scale-up interconnect).

The company positions Napier as fully air-cooled, operating at 30 kW per pod, which it states removes the need for liquid-cooling infrastructure and allows deployment in a broad range of data centers. Stated system capabilities include 608 PFLOPS of dense compute per rack, per-user throughput above 1,000 tokens per second, real-time 4K video generation at 30 FPS, and serving of multi-trillion-parameter Mixture-of-Experts models using EP72 parallelism and TDN Link, which the company claims runs giant models at twice the speed of leading solutions. Models can be run in 16-bit precision. Software integration is offered through PyTorch, Triton and vLLM support within Kubernetes-managed stacks.

Business model

Tensordyne designs and supplies AI inference systems — chips, compute trays, interconnect and accompanying software stack — manufactured through foundry partner TSMC and offered to datacenter operators and enterprises for deployment in their own facilities.

Latest developments

Tensordyne announced Napier and reported completing tapeout of its 3nm Napier chip with Broadcom and TSMC, with silicon transitioning into high-volume manufacturing at TSMC in 2026. It also states that models such as DeepSeek-V4 and larger MoE architectures are targeted workloads.

▸Full profile — market position, technology, go-to-market, geography, history

Market position

Tensordyne competes in datacenter AI inference silicon and systems, positioning its log-math architecture against GPU-based inference infrastructure on cost, energy efficiency and latency.

The company differentiates on logarithmic math-based compute and its scale-up interconnect, claiming higher energy efficiency than GPU architectures, air cooling instead of liquid cooling, and cited figures including 608 PFLOPS of dense rack compute, over 1,000 tokens per second per user, and 2x the speed of leading solutions on large MoE models, while retaining full 16-bit precision.

Technology

The architecture is based on logarithmic mathematics for AI compute, protected by patents first filed in 2019, combined with a low-latency, any-to-any cell-based scale-up interconnect (TDN LINK) enabling linear scaling. Napier chips are fabricated on a 3nm process with Broadcom as design partner and TSMC as foundry; the earlier Scorpio generation used a 7nm process. The system is disaggregated to reduce bottlenecks in multi-trillion-parameter model serving, air-cooled at 30 kW per pod, supports 16-bit precision inference, and integrates with PyTorch, Triton and vLLM.

Go-to-market

Direct engagement via the company website, with named product and sales contacts offering booked calls for different customer segments, and a planned technical whitepaper on the Napier system.

Hyperscalers building large-scale inference deployments; "neo cloud" providers serving high-margin, low-latency inference; enterprises running frontier models on-premises; and application-layer companies and foundation model builders.

Geography

Dual presence in North America and Europe, with a US office at 1195 Bordeaux Dr, Sunnyvale, CA 94089 and a German office at Brienner Strasse 59, Munich 80333.

History

The company filed its first five foundational patents on log-math-based architectures in 2019 and began designing Scorpio, its first-generation chip. Scorpio was taped out in 2021 with Broadcom, with functional 7nm silicon received from TSMC, validating the log-math architecture in hardware. In 2022 functional Scorpio samples shipped to initial validation customers, including a development system performing surround-view object detection. During 2023 the company extended support to transformer-based models and identified opportunities in generative AI workloads such as GPT and Stable Diffusion. In 2024 it halted its legacy vision tracks and refocused entirely on Napier, a datacenter AI inference chip, and entered a technology partnership with Juniper Networks to integrate scale-up networking components. Through 2025 the company optimized silicon, systems and software for Mixture-of-Experts models and agentic workloads, citing industry shifts such as DeepSeek-R1. In 2026 it completed tapeout of a 3nm Napier chip with Broadcom and TSMC and stated that Napier silicon was transitioning into high-volume manufacturing at TSMC.

Compiled by commissioned research from 2 cited public sources — announcements, filings, and press listed under research sources below.

Key figures

latest reported
Dense compute per rackJan 2026608 PFLOPS
Foundational patents filedJan 20195 patents
HeadcountAug 2026119
Per-user inference throughputJan 2026exceeding 1,000 tokens per second per user
Power per podJan 202630 kW
Real-time video generationJan 20264K content generated at 30 FPS
Video generation capabilityJan 20264K content generated at 30 FPS

Company-reported or press-reported figures, each dated to when it was claimed — not independently audited.

Timeline · 14

launches, deals, and filings
Jan 2026
Napier silicon enters high-volume manufacturing at TSMC

Napier silicon transitioned from development into high-volume manufacturing at TSMC facilities.

source ↗

Jan 2026
3nm Napier chip taped out with Broadcom and TSMC

The company completed the netlist and tapeout of its 3nm Napier chip in partnership with Broadcom and TSMC, targeting multi-modal generative AI inference.

source ↗

Jan 2026
3nm Napier chip taped out

Completed the netlist and tapeout of the 3nm Napier chip in partnership with Broadcom and TSMC for multi-modal generative AI inference.

source ↗

Jan 2025
Silicon, system and software optimization for MoE and agentic workloads

Throughout 2025 the company optimized its silicon, systems and software for Mixture-of-Experts models and agentic AI workloads.

source ↗

Jan 2025
Silicon, system and software optimization for MoE and agentic AI

Throughout 2025 the company optimized silicon, systems and software for Mixture of Experts models and agentic workloads.

source ↗

Jan 2024
Strategic pivot to datacenter-scale AI inference

The company halted its legacy vision product tracks and refocused engineering on Napier, a next-generation datacenter AI inference chip.

source ↗

Jan 2024
Strategic technology partnership with Juniper Networks

Partnership to integrate Juniper Networks scale-up networking components with the Tensordyne platform for fabric scalability in LLM clusters.

source ↗

Jan 2024
Technology partnership with Juniper Networks

Entered a strategic technology partnership with Juniper Networks to integrate scale-up networking components with its platform for fabric scalability in LLM clusters.

source ↗

Jan 2023
Support extended to transformer and generative AI workloads

While developing its second-generation architecture, the company added support for transformer-based models and evaluated generative AI workloads such as GPT and Stable Diffusion in simulation.

source ↗

Jan 2022
Scorpio samples shipped to first validation customers

Functional Scorpio samples were delivered to initial validation customers, including a development system running surround-view object detection continuously.

source ↗

Jan 2021
Scorpio first-generation chip taped out; functional 7nm silicon received

Scorpio was taped out with Broadcom and functional 7nm silicon was received from TSMC, validating the log-math architecture in hardware.

source ↗

Jan 2021
First-generation Scorpio chip taped out; functional 7nm silicon received

Scorpio was taped out with Broadcom and fully functional 7nm silicon was received from TSMC, validating the log-math architecture in hardware.

source ↗

Jan 2019
First five foundational log-math patents filed; Scorpio design begins

The company filed its first five foundational patents covering log-math-based AI compute architectures and started design of Scorpio, its first-generation chip.

source ↗

Jan 2019
First five foundational log-math patents filed; Scorpio chip design begins

The company filed its first five foundational patents for log-math-based architectures and started design of Scorpio, its first-generation chip.

source ↗

Dated company events from announcements, filings, and press; legal rows summarize public dockets and regulator releases.

▸Research sources · 2

primary sources listed

2 public sources were cited for this profile; the first-party ones are listed here.

Frequently asked questions

What does Tensordyne do?
Tensordyne builds logarithmic-math AI inference systems, led by its air-cooled Napier datacenter platform.
Who founded Tensordyne?
Tensordyne was founded by RK Anand, Gilles Backhus, R K Anand.
Who are Tensordyne's investors?
Tensordyne's investors include Banyan Ventures, BMW i Ventures, Bosch Ventures, Celesta Capital, Dns Capital, GreatPoint Ventures, Ineffable Ventures, Linden Capital and 6 more.
How much funding has Tensordyne raised?
Tensordyne has disclosed $102M raised across 1 of its 4 known rounds.
Where is Tensordyne headquartered?
Tensordyne is headquartered in Sunnyvale, US.