Recogni

Market position

The company positions its logarithmic-math compute approach and low-latency scale-up interconnect as delivering higher speed and energy efficiency than GPU architectures, citing claims of serving giant Mixture-of-Experts models at twice the speed of leading solutions, per-user throughput above 1,000 tokens per second, and air cooling instead of liquid cooling for data center deployment.

Technology

The architecture is built on logarithmic mathematics (TDN Math) applied to AI compute, paired with a low-latency, any-to-any cell-based scale-up interconnect (TDN LINK) for linear scaling across the system. Hardware includes the Napier chip (TDN AIP), fabricated at 3nm by TSMC with design work in partnership with Broadcom, and a compute tray (TDN ACT). The full rack-scale system is air-cooled at about 30 kW per pod, avoiding liquid cooling infrastructure, provides 608 PFLOPS of dense compute per rack, uses disaggregation to address bottlenecks when serving multi-trillion-parameter models, and runs models in 16-bit precision. Software compatibility covers PyTorch, Triton and vLLM within Kubernetes-managed environments. The predecessor first-generation Scorpio chip was built on a 7nm TSMC process.

Go-to-market

The website directs prospective customers to named product and sales contacts, with separate entry points for application-layer companies and foundation model builders on one side and hyperscalers and neo clouds on the other. It also offers a sign-up for a forthcoming technical system deep-dive whitepaper.

Three customer segments are addressed: hyperscalers building large-scale inference infrastructure, "neo clouds" serving high-margin, low-latency inference, and enterprises deploying on-premises AI systems. Application-layer companies and foundation model builders are also named as audiences.

Geography

Offices in the United States (1195 Bordeaux Dr, Sunnyvale, CA 94089) and Germany (Brienner Strasse 59, Munich, 80333), with the company describing a dual North America and Europe presence.

History

The company filed its first five foundational patents for log-math-based architectures in 2019 and began design of Scorpio, a first-generation chip intended to demonstrate logarithmic mathematics for AI acceleration. Scorpio was taped out in 2021 with Broadcom, with functional 7nm silicon received from TSMC, and functional samples were shipped to initial validation customers in 2022, including a development system performing surround-view object detection. During 2023 the company extended support to transformer-based models and identified opportunities in generative AI workloads such as GPT and Stable Diffusion. In 2024 it halted its legacy vision tracks to focus entirely on Napier, its data center AI inference chip, and entered a technology partnership with Juniper Networks for scale-up networking. Through 2025 it optimized silicon, systems and software for Mixture-of-Experts and agentic workloads. In 2026 it completed tapeout of a 3nm Napier chip with Broadcom and TSMC and began transitioning Napier silicon into high-volume manufacturing at TSMC.