Xcena
12 known investors
XCENA develops computational memory hardware that combines high-capacity pooled DDR5 memory with near-data processing (NDP) cores, built on the open Compute Express Link (CXL) standard to expand memory beyond CPU limits and run computation where data resides. It targets data center infrastructure for the AI era, serving hyperscalers, telcos, and research institutions with hardware plus a full-stack software SDK.
Also known as MetisX Β· XCENA Β· μμλ
Founders & leadership
Investors Β· 12
Also in the syndicate Β· 10
Valuation Β· disclosed
Disclosed eventsSource: SEC prospectus filings, and round valuations the company or its investors disclosed β follow each entry's link for the claim.
Company profile
researched Aug 2026XCENA is a semiconductor company developing computational memory for data center and AI infrastructure. Its architecture combines high-capacity pooled DDR5 memory with near-data processing (NDP) cores on the open Compute Express Link (CXL) standard, so that routine data operations execute inside the memory module rather than requiring round trips between memory, CPUs and GPUs. The company positions this as addressing memory scaling in AI inference, including preprocessing, KV cache management and data caching, which typically run on CPUs.
The flagship product, MX1, is described by the company as the world's first CXL 3.2 computational memory device. Published specifications include a CXL 3.2 Type 3 HDM-DB host interface over PCIe 6.0 dual x8 with NVMe, a PCIe 6.0 dual x4 device-side interface, four DDR5 RDIMMs at 8,400 MT/s in a 2DPC configuration for up to 2 TB of memory, thousands of custom 1.4 GHz RISC-V cores with FP32/FP16 vector engines, a dual-core Cortex-A53 management processor, in-line AES-XTS 256 encryption, an LZ4 hardware decompression engine with software compression on the RISC-V cores, Chipkill and multi-bit error detection with DRAM ECC and SSD RAID, and an InfiniteMemory feature that adds petabyte-scale expansion through a separate PCIe 6.0 root complex connection to SSDs. The product is offered in an FHHL double-width add-in-card module, and some listed features are noted as planned for production silicon.
Alongside the hardware, XCENA provides a full-stack SDK with multi-level APIs, simulation tools and drivers for major operating systems. High-level runtime APIs are intended to let applications use CXL computational memory without major architectural changes, while low-level device APIs allow fine-grained control of data movement and compute execution.
Founding story
Jin Kim co-founded the company in 2022 with Dohun Kim and Harry Juhyun Kim, all veterans of Samsung and SK hynix. The founding thesis, as described by the CEO, is that CPUs and GPUs have grown more capable over decades while memory has not, and that AI inference is increasingly a memory scaling problem rather than purely a compute problem.
Business model
XCENA designs and sells computational memory hardware, with mass-production chips planned from Samsung foundry lines by the end of 2026 and revenue expected to begin in 2027; the hardware is accompanied by a full-stack software SDK, drivers and simulation tools intended to ease customer adoption. As of mid-2026 the MX1 was a prototype being explored with selected partners to validate real-world performance and system-level efficiency gains.
Revenue is expected to come from sales of computational memory hardware, with the company projecting the start of revenue in 2027 following mass production of the MX1 at the end of 2026.
Traction
More than 90 staff across Pangyo and Sunnyvale as of May 2026; $185 million raised in total; MX1 prototype under evaluation with select partners; mass production targeted for end-2026 with revenue expected from 2027; named an investment company of the year at the Korea VC Awards 2024.
Latest developments
In late May 2026 XCENA announced a $135 million Series B at a $570 million post-money valuation, co-led by Atinum Investment and IMM Investment with a broad syndicate of existing and new Korean investors plus Corstone Asia, taking total funding to $185 million; the company said it was also in discussions with international investors about additional funding. MX1 remained a prototype, with mass-production chips scheduled from Samsung's foundry by the end of 2026 and first revenue expected in 2027.
βΈFull profile β market position, technology, go-to-market, geography, history, risks & controversies
Market position
XCENA targets the memory-centric layer of AI infrastructure rather than competing with NPU vendors on training accelerators. Its stated closest rivals are Nasdaq-listed Astera Labs and Marvell, both working on next-generation memory connectivity, with Marvell described as a large, established player in the same space.
Management cites intellectual property and vertical integration as the main differentiators against next-generation memory connectivity rivals: XCENA integrates thousands of small, data-processing-optimized RISC-V cores, compared with what it describes as a handful of general-purpose cores in a competitor's publicly documented approach, and designs its own internal memory hierarchy, interconnect bus and DRAM controller rather than outsourcing those blocks. The company also markets MX1 as the first CXL 3.2 computational memory product and claims workloads that previously required ten servers could potentially run on one.
Technology
Computational memory built on CXL: a CXL 3.2 Type 3 HDM-DB device with back-invalidate support, PCIe 6.0 dual x8 host interface, CXL 3.2-compliant coherency and hot-page monitoring for memory tiering; near-data processing using thousands of custom RISC-V cores at 1.4 GHz with FP32/FP16 vector engines and an LLVM-based custom toolchain; up to 2 TB of DDR5 RDIMM capacity (256 GB DIMMs, 2DPC) at 8,400 MT/s; hardware LZ4 decompression plus software compression; in-line AES-XTS 256; enhanced RAS with Chipkill, multi-bit error detection, DRAM ECC and SSD RAID; and InfiniteMemory, which uses an integrated PCIe 6.0 root complex and attached SSDs for petabyte-scale expansion. Supported CXL features listed include BI, CHMU, MH-MLD, PBR, DCD, IDE and TSP. A full-stack SDK provides high-level runtime APIs, low-level device APIs, simulators and OS drivers.
Go-to-market
XCENA sells directly to large infrastructure operators and works with select partners on MX1 evaluations, while discussions with several global memory vendors were reported to be at an early stage as of May 2026. Series B proceeds are earmarked for global expansion, scaling customer deployments and advancing the computational memory product. The SDK, sample requests and documentation serve as adoption channels for prospective customers.
Hyperscalers, telecommunications operators and research institutions. The company describes its ideal customers as hyperscalers spending tens of billions of dollars a year on AI infrastructure, where small memory-efficiency gains translate into large savings.
Geography
South Korea and the United States. Korean sites are in Pangyo, Bundang-gu, Seongnam-si, Gyeonggi-do (20 Pangyo-ro 241beon-gil and 670 Daewangpangyo-ro), and the U.S. office is at 530 Lakeside Drive, Suite 240, Sunnyvale, California; one report describes the company as Santa Clara, California-based.
History
The company was co-founded in 2022 by CEO Jin Kim with CTO Dohun Kim and CPO Harry Juhyun Kim. It originally operated under the name MetisX and later rebranded to XCENA, a change the company framed as reflecting its mission to redefine memory. It was named an investment company of the year at the Korea VC Awards 2024. In May 2026 it announced a $135 million Series B at a $570 million valuation, bringing total funding to $185 million.
Risks & controversies
The lead product was still a prototype as of May 2026, with mass production and first revenue dependent on 2026-2027 milestones at Samsung's foundry. Customer engagements with global memory vendors were described as early-stage and unnamed, and the company competes with substantially larger, publicly listed suppliers in memory connectivity.
Compiled by commissioned research from 8 cited public sources β announcements, filings, and press listed under research sources below.
Key figures
latest reportedCompany-reported or press-reported figures, each dated to when it was claimed β not independently audited.
Timeline Β· 5
launches, deals, and filingsXCENA announced a $135 million Series B at a $570 million valuation, co-led by Atinum Investment and IMM Investment with Corstone Asia and existing investors including SBI Investment and Mirae Asset Capital; total raised reached $185 million. Proceeds are for global expansion, scaling customer deployments and advancing its computational memory product.
$135M source β
The company officially changed its corporate name from MetisX to XCENA as part of a rebranding effort, which it said reflects its mission to redefine memory.
XCENA presented MX1, described as the world's first CXL 3.2 computational memory device, with a PoC product brief and sample requests. The chip was still a prototype as of May 2026, with mass-production chips scheduled from Samsung foundry lines by the end of 2026 and revenue expected from 2027.
The company (μμλ) was selected as an investment company of the year at the Korea VC Awards 2024.
CEO Jin Kim co-founded the startup in 2022 with CTO Dohun Kim and CPO Harry Juhyun Kim, all previously at Samsung and SK hynix.
Dated company events from announcements, filings, and press; legal rows summarize public dockets and regulator releases.
βΈResearch sources Β· 8
primary sources listed
- Xcenaxcena.com Β· web
8 public sources were cited for this profile; the first-party ones are listed here.
Frequently asked questions
- What does Xcena do?
- XCENA builds CXL-based computational memory chips that pair pooled DDR5 capacity with near-data processing cores for AI data centers.
- Who founded Xcena?
- Xcena was founded by Jin Kim.
- Who are Xcena's investors?
- Xcena's investors include Atinum Investment Co. Ltd., Kiwoom Investment.