Codasip

Codasip develops RISC-V processor IP and processor design tooling, positioning its portfolio around silicon-level security. The company implements CHERI technology in its RISC-V cores, adding protection against out-of-bounds memory accesses to guard against cyberattacks arising from software defects or malicious code, and describes itself as the first to offer a commercial CHERI RISC-V 64-bit application core. CHERI is presented as an open standard with over 15 years of development that addresses the root cause of approximately 70% of critical vulnerability exposures (CVEs) through an architectural rather than reactive defense.

The product and tooling portfolio includes the Codasip Studio processor design environment, used to manage processor IP variants and processor co-design through an Exploration Framework, an exploration platform aimed at CHERI adoption, and cores such as the L150 embedded core (demonstrated with CORDIC acceleration for motor control) and the CHERI-enabled 700 family. Codasip frames its approach as "Custom Compute" and "Bounded Customization," delivering both standard silicon and customer-tailored secure systems and platforms.

Business model

Codasip licenses processor IP and design tooling to semiconductor and system companies, including licensing agreements for specific cores such as the CHERI-enabled embedded CPU from its 700 family licensed to EnSilica. It also offers customer-tailored secure systems and platforms alongside standard silicon products, and sells a productized offering marketed as Codasip Prime.

Revenue is derived from licensing processor IP and design tools, including licensing agreements for individual cores, plus tailored secure system and platform engagements.

Traction

Codasip reports a licensing agreement with EnSilica for a CHERI-enabled embedded CPU from its 700 family, ASIL-D certification of its RISC-V processors, deployment of a custom vector processor in the SYCLOPS edge AI project, and case studies covering motor control with IAR and L150-based CORDIC acceleration.

Latest developments

In April 2025 Codasip launched an exploration platform to accelerate CHERI adoption. On 1 July 2025 the company's board announced it had initiated an expedited process to sell the company. In October 2025 Codasip said its RISC-V processors had been certified up to ASIL-D, and in November 2025 it announced a strategic licensing agreement with EnSilica for a CHERI-enabled embedded CPU from its 700 family, as well as the use of a custom vector processor in the SYCLOPS edge AI project. On 8 April 2026 the company announced a strategic pivot and divestiture.